1. Field of the Invention
The present invention relates to the design of current mode digital/analog converters (DACs). In particular, the present invention relates to the design of a current mode DAC having a power consumption which scales with variations in operating sampling speed and resolution.
2. Description of the Related Art
A conventional current mode DAC is typically designed for a particular combination of sampling speed and resolution, and is not optimized across a wide range of such parameter values. That is, although such a DAC can operate with a lower effective resolution or run at a lower speed simply by turning off bit inputs or by lowering the clock input rate, the power consumed by the DAC does not scale appropriately with the parameter variation to be comparable to a custom-designed DAC for the lower resolution or the lower clock rate.
The present invention provides a method and a structure of a current mode segmented digital/analog converter (xe2x80x9cDACxe2x80x9d) that scales power consumption over wide ranges of resolutions and sampling rates.
According to the present invention, the DAC of the present invention scales power consumption with the variation in sampling rate, by varying the currents in the current sources, by selectively enabling and disabling current sources in the MSB and the LSB segments of the DAC, or both. In one embodiment, by selectively enabling and disabling current sources, the time constants at the switching node can remain unchanged by maintaining substantially constant current densities. In another embodiment, a phase-locked loop circuit tracks the sampling rate, and the output voltage of the phase-locked loop controls the current in the current sources of the DAC in proportion with the variation in sampling rate.
According to the present invention, the DAC of the present invention scales power consumption with the variation in the required resolution of the DAC, by varying the currents in the current sources, by selectively enabling and disabling current sources in the MSB and the LSB segments of the DAC, or both. In one embodiment, the currents in the current sources of the DAC are varied according to a change in resolution. In another embodiment, the current sources in the MSB segment of the DAC are selectively enabled or disabled in accordance with the change in resolution. In this second embodiment, because the current densities in the current sources can remain substantially constant, the time constants of the DAC can remain unchanged.
Thus, according with one embodiment of the present invention, a current mode segmented DAC of a maximum resolution N includes: (a) a first segment of the DAC receiving M input bits; (b) a second segment of the current mode segmented DAC receiving L input bits, such that the total number of bits M+L exceed the required maximum resolution N; and (c) a control circuit that enables and disables the current sources in the first and second segments. In one implementation, for static linearity reasons, the first segment current sources are thermometer encoded, while the second segment current sources are subdivided into a thermometer encoded group and a binary encoded group.
According to another aspect of the present invention, the currents in DAC current sources are adjustable in response to a bias voltage, so that when the bias voltage is set according to a variation of a performance parameter (e.g., sampling rate or a change in resolution), the power consumption of the DAC is adjusted to scale with the change in parameter. In one embodiment of the present invention, the currents in the DAC are set from a circuit including a phase-locked loop and a linear transconductor.
According to another aspect of the present invention, the output voltage swing at the output terminals of the DAC is maintained by relating the voltage at an external resistor to a virtual resistor at the output terminals of the DAC. The voltage at the external resistor is set by a variable bias voltage of a current source coupled in series with the external resistor.